VIA Nano Processor Platform: Key Features 64-bit Next Generation Architecture The superscalar, speculative out-of-order 'Isaiah, architecture of the VIA Nano processor family supports a full 64-bit instruction set and provides for macro-fusion and micro-fusion functionality, and sophisticated branch prediction for greater processor efficiency and performance. Performance Efficiency The VIA Nano processor has been designed from the ground up to offer excellent thermal management properties and superb power efficiency. With the lowest power draw in the industry, the VIA Nano processor is the only 64-bit, out-of-order architecture processor suited to low power, high density applications and environments. High-Performance Computation and Media Processing A high-speed, low power VIA V4 Front Side Bus starting at 800MHz coupled with a high floating point unit, support for new SSE instructions, and two 64KB L1 caches and 1MB exclusive L2 cache with 16-way associativity offers huge gains in multimedia performance, including the latest multimedia and HD video codecs. High-Performance Floating-Point Execution The VIA Nano processor has been designed with significant emphasis on high-performance floating-point execution, using a completely new algorithm for floating-point adds that results in the lowest floating-point add latency of any x86 processor. Similarly, the floating-point multiplier has the lowest latency of any x86 processors. |
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